Historically, scan synchronization for optical scanners has been performed by detecting and generating a signal pulse at the instant that the scanning spot crosses a fixed point, generally called Start Of Scan (SOS). This SOS pulse is used to synchronize a stable, gated clocking oscillator, which, in turn, controls the flow of pixel data into the beam modulator. If the spot velocity is constant and consistent, the printer pixel density is constant for each line. If the spot velocity varies, as caused by polygon motor "hunting", or if the oscillator has a tendency to drift, the resulting printed pixel density would vary accordingly, in the scan direction. This pixel placement error is generally referred to as jitter, particularly when varying errors occur in adjacent, or closely spaced scan lines.
To reduce such jitter problems, it has been customary, as shown in FIG. 1, to include a split detector at the End Of Scan (EOS), which in conjunction with the SOS split detector, a pixel counter, and phase detector, provides a measure of any error between the spot velocity and pixel clock frequency. Specifically, referring to FIG. 1, an SOS signal generated by a conventional SOS split detector pulse circuit 2 gates on a voltage controlled oscillator (VCO) clock generator 4 of conventional construction and starts the counting of the SOS to EOS interval clock counter 6. Counter 6 has stored therein the number of pixels which are desired for the interval between SOS and EOS, and when that number of clock pulses is received from the output of oscillator 4 an End of Count (EOC) signal is generated and applied to one input of a phase detector or comparator 8 of conventional construction. The second input to phase detector 8 is the EOS signal generated by EOS split detector pulse circuit 10. Detector pulse circuits 2 and 10 are shown schematically in their simplest form in FIG. 1a in which photodetectors #1 and #2 represent respective halves of the split detector. FIG. 1a also shows the outputs of photodetectors #1 and #2 and the output of the difference amplifier. Note that detectors #1 and #2 are back biased to reduce detector capacitance and that load resistors R.sub.L are provided for high speed operation. Phase detector 8 is a temporal comparator which provides, by phase comparison, an output signal having a width or length equal to or proportional to the timing difference between the EOS and the EOC signals. Phase detector 8 has two output terminals providing "pump signals" in accordance with the phase comparison; a pump signal of proper width appearing at the "UP" output terminal if the EOS signal precedes the EOC signal in phase and a pump signal of the proper width appearing at the "DOWN" terminal if the EOS signal lags the EOC signal in phase. The pump up or pump down signals are applied to a differential integrator 12 of conventional construction which integrates up or down to vary its output voltage amplitude change proportionally to the width of the input pulse at any one time, thereby providing an error signal representative of the timing difference between the spot velocity and the pixel clock frequency.
The timing of the EOS and EOC pulses received at the inputs of phase comparator 8, together with the timing of the "pump up" and "pump down" output pulses from the phase comparator 8 that are delivered to the integrator 12, together with the integrator output voltage waveform may be as shown as in FIG. 1b as an example of the relationships of these signals. For facet #1 and facet #2 the EOS pulses precede the EOC pulses indicating that the VCO pixel clock frequency was too low for the spot velocity during those scans, and causing the generation of "pump up" pulses by the phase comparator 8. For facet #3 the EOS pulse lags the EOC pulse indicating that the pixel clock frequency was too high for the spot velocity during that scan and causing the generation of a "pump down" pulse by the phase comparator 8. This sequence continues for each of the facets in turn, generating the appropriate "pump up" and "pump down" pulses in accordance with the spot velocity and pixel clock frequency, and repeating each revolution of the polygon.
If the pixel clock frequency is consistently low during a series of scans such as for a number of polygon revolutions, then the integrator output voltage will be "pumped" up consistently, whereas if the pixel clock frequency is consistently high during a series of polygon revolutions, then the integrator output will be "pumped" down consistently. The integrator 12 output is applied to the gated VCO 4 via a low pass filter 14 and combining circuit 16 such that when the pixel clock frequency is low and the integrator output is "pumped" up this change in the control voltage that is applied to the VCO will increase the pixel clock frequency that is generated by the VCO 4. Conversely, when the pixel clock frequency is high and the integrator output is "pumped" down this change in the control voltage that is applied to the VCO will decrease the pixel clock frequency that is generated by the VCO 4. This phase locked feedback provides the means whereby the pixel clock frequency is maintained in accordance with the spot velocity and the number of pixels that are desired to be placed between the SOS and EOS detector spacing.
Properly implemented, this phase locked loop provides long term stability for relatively low frequency fluctuations. This low frequency response limitation is due to the delay that is intrinsic to the technique, i.e., the change in the correcting error signal that is developed is based on the scan that has just been completed, and cannot correct the error in the scan that produced this change. Thus, the feedback correction that is based on one scan, can only be applied to the next scan, and those scans that follow. This delay represents a phase shift, and as such, limits the unity gain bandwidth that can be achieved without causing loop instability and oscillations.
The function of the low pass filter 14 is to provide the bandwidth limit which is necessary to achieve a stable loop. However, there are scan to scan cyclic spot velocity errors that are beyond this bandwidth but must still be corrected. These cyclic errors, caused by differences in the polygon facets, or by the polygon motor cogging, are called "signature" or "synchronous" errors because of their unique, but repetitive nature, i.e. one cycle per polygon revolution.
This "signature" error signal is composed of square wave segments, each segment representing the spot velocity error that is produced by its respective facet. Having one segment per facet, and repeating every revolution of the polygon, the lowest information frequency of this "signature" waveform will be equal to the polygon speed (RPS). The highest information frequency of this "signature" waveform will be equal to the RPS frequency times the number of facets on the polygon divided by two. All other information frequencies that may be present in the "signature" waveform will be in accordance with the combinations of the amplitudes of these segments, i.e. they will be synchronous harmonics of the polygon rotation, all other frequencies are considered to be noise. Because of the nature of this "signature" error signal, it can be filtered, stored, phase shifted, and summed back into the feedback loop, and can thereby reduce the effects of such scan to scan spot velocity "signature" errors. A description of this signal processing follows.
Returning to FIG. 1, band pass filter 18, with gain in the frequency range of the "signature" waveform, receives the error signal of integrator 12 and outputs an amplified a-c error correction signal to a switched filter circuit 20 having a single input resistor and capacitors equal in number to the number of facets of the scanner polygon, i.e. one capacitor per facet. Referring to FIG. 1c, the filter circuit 20 is seen to contain for an 8 facet polygon, for example, an 8 contact electronic switch 24 (shown as its mechanical equivalent for simplicity) that demultiplexes the input signal to 8 capacitors C, and a second 8 contact electronic switch 26 (also shown as its mechanical equivalent for simplicity) that re-multiplexes the capacitor voltages into the single output terminal of the switched filter circuit 20. The electronic switch 24 forming part of the filter circuit 20 applies the a-c error correction signal in succession to the individual input terminals of the filter elements, in synchronism with the polygon facets, thus in synchronism with the segmented error waveform.
While the input signal is applied to a capacitor via the resistor R and switch 24, it forms a low pass RC circuit, and the voltage on the capacitor will change in accordance with the RC time constant and the voltage at the input at that time. When the input switch 24 is open, the capacitor is isolated, and the voltage that was impressed on it at the termination of the charging interval remains, i.e. the capacitor now acts as a storage element, until once again that particular switch element closes, and again connects that capacitor to the same segment of the next cycle of the signature waveform.
The RC time constant that the resistor R forms with each capacitor C in turn, is long relative to the rotational speed of the polygon, taking many revolutions of the polygon for each capacitor to reach a voltage that is close to the voltage of its respective segment of the input waveform. The effective RC time constant is actually longer than the product of resistance and capacitance, as each capacitor is charging for only part of the time. Thus, the effective time constant can be artificially lengthened by allowing each input switch element to close for a time that is shorter than the actual input waveform segment.
The electronic switch 24 that forms a part of the filter input circuit as described above, has an output counterpart, i.e. a switch 26 that connects the filter/storage capacitors to the output terminal in a sequential manner as with the input switch elements. The voltage output from this second switch is thus a recreation of the input waveform except that it has been filtered of all frequencies that are not synchronous with the polygon rotation or harmonics thereof, in accordance with the number of facets. Also, the timing of the input and output switches being controlled by the SOS signal and being such that when an input terminal of one filter element is receiving the a-c error correction signal the output terminal of the next preceding filter element is being accessed. Thus not only is the input waveform filtered of all extraneous frequencies but it is also delayed by one whole revolution of the polygon less the delay of one facet. This delay is an important aspect of the switched filter as it compensates for the phase shift that is caused by the delay that is inherent in the generation of the error signal, and was the cause for limiting the loop bandwidth with the low pass filter 14.
If at the start of scan a voltage is applied to the VCO such to cause the generation of a frequency that is too low to generate the prescribed number of pixels in that scan, then at the end of scan the phase detector generates a "pump up" signal that increases the VCO applied voltage in an attempt to correct that error. As previously described, this new correction voltage comes too late to make the correction for that facet. This delay of the correction signal represents the phase shift that limits the loop bandwidth that can be used for error correction. However, introducing additional delay, i.e. by delaying the error correction signal one full cycle, less the delay of one facet that is already present, then the error correction signal will now be in phase again, by virtue of the fact that a 360 degree phase shift of a repetitive wave form is the same as no phase shift at all. This delayed signal from the switched filter or auxiliary loop, herein called an "S" circuit, can now be used in a feedback manner to compensate for the "signature" errors and thereby reduce such errors by an order of magnitude or more.
Synchronization of the pixel clock to the spot velocity, using the techniques described above, have been successful for achieving scan to scan registration of exposure profiles to a consistent accuracy of one part in 20,000. The remaining jitter is primarily random, having a frequency range from a fraction of a hertz, up to one half the scan frequency. (Jitter frequencies that are higher than half the scan rate manifest themselves as a lower beat frequency.) Recent work has indicated the possibility of reducing the sources of these errors, such as shielding the electronics and VCO from external noise sources. However, there are practical limits, as well as theoretical limits to which these random or non synchronous sources of jitter can be reduced.
One method (and often the only method) of reducing the effects of noise in a system, is by reducing the bandwidth. The high bandwidths needed by the synchronizing techniques used in the past (FIG. 1), arise from the need to synchronize a pixel clock at the start of scan, the need for a high speed comparator at the end of scan, and the need for a low Q VCO that can be gated on rapidly. Although the circuit of FIG. 1 utilizes all of the above high speed circuits, it is interesting and significant to note that the control loop for the VCO has a very low bandwidth relative to the bandwidths mentioned above, this bandwidth limitation being necessary in order to achieve loop stability, but it is also effective in reducing the effects of noise in that particular circuit function.
It would be advantageous if the same type of bandwidth limiting techniques, as used in the EOS function, be used for the generation of the SOS synchronizing function as well, and the achievement of such is provided by the systems hereinafter described.